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AN32058A page 1 of 64 product standards features description AN32058A is 49 dots matrix led driver. it can drive up to 16 rgb leds. ? 7 x 7 led matrix driver (total led that can be driven = 49) ? built-in memory (rom and ram) ? ldo : 2-ch ? spi interface : 1-ch ? driver for rgb color unit : 1-ch ? 44 pin plastic quad flat non-leaded package (qfn type) applications x0~x6 vb vled1 vled2 y0~y6 ldo2 battery int rgbgnd pgnd agnd 1.0 ? f di do rstb 27 k ? ce clk ledctl iref b g r 7 7 ldocnt led ldo1 1.0 ? f vrefd 1.0 ? f cpu i/f http://www.semicon. panasonic.co.jp/en/ 7 x 7 dots matrix led driver lsi ? mobile phone ? smart phone ? pcs ? game consoles ? home appliances etc. typical application note) the application circuit is an example. the operation of the mass production set is not guaranteed. sufficient evaluation and verification is required in the design of the mass production set. the customer is fully responsible for the incorporation of t he above illustrated application circuit in the design of the equipment. d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 2 of 64 product standards contents ? features ??????????????????????????????? 1 ? description ??..??????????????????????????? 1 ? applications ????????????????????????????? 1 ? typical application ????????????????????????? 1 ? contents ??????????????????????????????? 2 ? absolute maximum ratings ????????????????????? 3 ? power dissipation rating ?????????????????????? 3 ? recommended operating conditions ???????????????.. 4 ? electrical characteristics .???????????????????? 5 ? pin configuration ??????????????????????????13 ? pin functions ..???????????????????????????? 14 ? functional block diagram ?????????????????????16 ? operation ?.????????????????????????????? 17 ? package information ???????????????????????? 63 ? important notice .?????????????????????????? 64 d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 3 of 64 product standards absolute maximum ratings ? v ? 0.3 to 3.4 ledctl, rstb, ce, clk, di input voltage range ? v ? 0.3 to 6.0 ldocnt ? v ? 0.3 to 3.4 int, do output voltage range ? v ? 0.3 to 6.5 r, g, b, ldo1, ldo2, x0, x1, x2, x3, x4, x5, x6, y0, y1, y2, y3, y4, y5, y6 ? kv 2.0 hbm (human body model) esd *2 ? c ? 30 to + 85 t opr operating ambience temperature *2 ? c ? 30 to + 125 t j operating junction temperature *2 ? c ?55to+125 t stg storage temperature *1 v 6.5 vled max note unit rating symbol parameter *1 v 6.0 vb max supply voltage 0.557 w 1.392 w 71.8 ? c /w 44 pin plastic quad flat non-leaded package (qfn type) p d (ta=85 ? c) p d (ta=25 ? c) ? ja package power dissipation rating note) for the actual usage, please refer to the p d -ta characteristics diagram in the package specification, follow the power supply voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not exceed the allowable value. caution although this ic has built -in esd protection circuit, it may st ill sustain permanent damage if not handled properly. therefore, proper esd precautions are recommended to avoid electrostatic damage to the mos gates note) this product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum rating. this rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than our stated recommended operating range. when subjected under the absolute maximum rating for a long time, the reliability of the product may be affected. *1 vb max = vb, vled max = vled1 = vled2. the values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2 except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for ta = 25 ? c. d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 4 of 64 product standards recommended operating conditions *1 v 4.6 3.7 3.1 vb supply voltage range *1 v 5.6 5.0 3.1 vled ? v 3.0 ? ?0.3 ledctl, rstb, ce, clk, di input voltage range *2 v vb + 0.3 ? ?0.3 ldocnt ? v 3.0 ? ?0.3 int, do output voltage range *2 v vled + 0.3 ? ?0.3 r, g, b, ldo1, ldo2, x0, x1, x2, x3, x4, x5, x6, y0, y1, y2, y3, y4, y5, y6 typ. min. note unit max. symbol parameter note) *1: the values under the condition not exceeding the above absolute maximum ratings and the power dissipation. do not apply external currents and voltages to any pin not spe cifically mentioned. voltage values, unless otherwise specified, are with respect to gnd. gnd is voltage for agnd, rgbgnd and pgnd. vb is voltage for vb. vled is voltage for vled1 and vled2. *2: ( vb + 0.3 ) v must not exceed 6 v. ( vled + 0.3 ) v must not exceed 6.5 v. d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 5 of 64 product standards ? ma 200 100 50 ldocnt = high reg18 = high v ldo1 = 0 v, ipt1 = i ldo1 ipt1 short circuit protection current ? ? a 12 8 ? at standby mode ldocnt = low ldo2 is active. icc2 current consumption (2) ? v 1.91 1.85 1.79 i ldo1 = ? 30 ma vl1 output voltage ? db ?40 ?45 ? vb = 3.6 v + 0.2 v[p-p] f = 1 khz i ldo1 = ? 15 ma psl11 = 20log (acv ldo1 / 0.2) psl11 ripple rejection (1) ? db ?25 ?35 ? vb = 3.6 v + 0.2 v[p-p] f = 10 khz i ldo1 = ? 15 ma psl12 = 20log (acv ldo1 / 0.2) psl12 ripple rejection (2) v v 0.64 1.27 reference current ? 0.54 0.44 i iref = 0 ? a viref output voltage voltage regulator (ldo1) ? ? a 24 18 ? ldocnt = high ldo1 and ldo2 are active. icc3 current consumption (3) ? 1.24 1.21 i vref = 0 ? a vref output voltage reference voltage current consumption ? ? a 1 0 ? at off mode ldocnt = low icc1 current consumption (1) limits typ unit max note min condition symbol parameter electrical characteristics vb = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 6 of 64 product standards ? mhz 1.44 1.20 0.96 ? fdc oscillation frequency ? ma 300 100 50 ldocnt = high v ldo2 = 0v ipt2 = i ldo2 ipt2 short circuit protection current ? v 2.94 2.85 2.76 i ldo2 = ? 30 ma vl2 output voltage ? ? 4.8 2 ? i y0, y1, y2, y3, y4, y5, y6 = 5 ma rscan = v y0, y1, y2, y3, y4, y5, y6 / 5 ma rscan resistance at the switch on ? db ?15 ?25 ? vb = 3.6 v + 0.2 v[p-p] f = 10 khz i ldo2 = ? 15 ma psl22 = 20log (acv ldo2 / 0.2) psl22 ripple rejection (2) scan switch oscillator voltage regulator (ldo2) ? db ?30 ?35 ? vb = 3.6 v + 0.2 v[p-p] f = 1 khz i ldo2 = ? 15 ma psl21 = 20log (acv ldo2 / 0.2) psl21 ripple rejection (1) limits typ unit max note min condition symbol parameter electrical characteristics (continued) vb = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 7 of 64 product standards ? ? a 1 ? ? current off setup v x0, x1, x2, x3, x4, x5, x6 = 4.75 v imxoff = i x0, x1, x2, x3 , x4, x5, x6 imxoff leakage current when matrix led turns off *1 ma 8.992 8.326 7.660 at 8 ma setup v x0, x1, x2, x3, x4, x5, x6 = 1 v imx8 = i x0, x1, x2, x3, x4, x5, x6 imx8 output current (4) *1 ma 4.490 4.157 3.824 at 4 ma setup v x0, x1, x2, x3, x4, x5, x6 = 1 v imx4 = i x0, x1, x2, x3, x4, x5, x6 imx4 output current (3) *1 ma 2.239 2.073 1.907 at 2 ma setup v x0, x1, x2, x3, x4, x5, x6 = 1 v imx2 = i x0, x1, x2, x3, x4, x5, x6 imx2 output current (2) *1 ma 1.116 1.033 0.950 at 1ma setup v x0, x1, x2, x3, x4, x5, x6 = 1 v imx1 = i x0, x1, x2, x3, x4, x5, x6 imx1 output current (1) ? % 5 ? ?5 the average value of all channels, and the current error of each channel imxch the error between channels current generator (for 7 ? 7 dots matrix led) *1 ma 16.914 15.661 14.408 at 15 ma setup v x0, x1, x2, x3, x4, x5, x6 = 1 v imx15 = i x0, x1, x2, x3 , x4, x5, x6 imx15 output current (5) limits typ unit max note min condition symbol parameter electrical characteristics (continued) vb = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. *1 : values when recommended parts (erj2rhd273x) are used for iref terminal. the other current settings are combination of above items. d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 8 of 64 product standards ? ? a 1 ? ? current off setup v r, g, b = 4.75 v irgboff = i r, g, b irgboff leakage current when rgb turn off *1 ma 8.816 8.163 7.510 at 8 ma setup v r, g, b = 1 v irgb8 output current (4) *1 ma 4.418 4.091 3.764 at 4 ma setup v r, g, b = 1 v irgb4 output current (3) *1 ma 2.220 2.056 1.892 at 2 ma setup v r, g, b = 1 v irgb2 output current (2) *1 ma 1.113 1.031 0.949 at 1ma setup v r, g, b = 1 v irgb1 output current (1) ? % 5 ? ?5 the average value of all channels, and the current error of each channel irgbch the error between channels current generator (for rgb color unit) limits typ unit max note min condition symbol parameter electrical characteristics (continued) vb = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. *1 : values when recommended parts (erj2rhd273x) are used for iref terminal. the other current settings are combination of above items. d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 9 of 64 product standards ? v ldo2 ? 0.2 (0.15 ) ? ? i int = 2 ma vddsel = ldo2 (i int = 0.5 ma ) vol1 output voltage of low-level (1) int ? v ? ? ldo1 ? 0.8 i int = ? 2 ma vddsel = ldo1 voh2 output voltage of high-level (2) ? ? a 1 0 ? v ledctl, rstb, csb, clk, di = 0 v iil = i ledctl, rstb, ce, clk, di iil input current of low-level ? ? a 1 0 ? v ledctl, rstb, ce, clk, di = 1.85 v iih = i ledctl, rstb, ce, clk, di iih input current of high-level ? v 0.4 ? ?0.3 low-level recognition voltage vil input voltage range of low- level ? v ldo2 + 0.3 ? ldo1 ? 0.8 high-level recognition voltage vih input voltage range of high- level ? v ldo1 ? 0.3 (0.15 ) ? ? i int = 2 ma vddsel = ldo1 (i int = 0.5 ma ) vol2 output voltage of low-level (2) spi i/f ledctl rstb ? v ? ? ldo2 ? 0.8 i int = ? 2 ma vddsel = ldo2 voh1 output voltage of high-level (1) limits typ unit max note min condition symbol parameter electrical characteristics (continued) vb = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 10 of 64 product standards do ? v ldo1 ? 0.2 ? ? i do = 2 ma vol output voltage of low-level ? ? a 1 0 ? v ldocnt = 0 v iil = i ldocnt iil input current of low-level ? ? a 1 0 ? v ldocnt = 3.6 v iih = i ldocnt iih input current of high-level ? v 0.4 ? ?0.3 low-level recognition voltage vil input voltage range of low-level ? v vb + 0.3 ? vb ? 0.7 high-level recognition voltage vih input voltage range of high-level ldocnt ? v ? ? ldo1 ? 0.8 i do = ? 2 ma voh output voltage of high-level limits typ unit max note min condition symbol parameter electrical characteristics (continued) vb = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 11 of 64 product standards max typ note unit limits condition symbol parameter min *2 *3 ms ? 5 ? time until output voltage reaches to 10% tsd2 fall time i ldo1 = ? 15 ma ? ? 50 ? a(1 ? s) i ldo1 = ? 50 ? a ? ? 15 ma (1 ? s) ? time until output voltage reaches to 10% time until output voltage reaches to 0 v to 90% *2 *3 ms ? 0.25 ? time until output voltage reaches to 0 v to 90% tsu2 rise time *3 ma ? 15 ? ? iomax2 maximum load current *3 mv ? 70 ? i ldo2 = ? 50 ? a ? ? 15 ma (1 ? s) vtr21 load transient response (1) *3 mv ? 70 ? i ldo2 = ? 15 ma ? ? 50 ? a(1 ? s) vtr22 load transient response (2) tsd (thermal shutdown circuit) *2 *3 ms ? 0.25 ? tsu1 rise time *2 *3 ms ? 5 ? tsd1 fall time *3 ma ? 15 ? iomax1 maximum load current *3 mv ? 70 ? vtr11 load transient response (1) *3 mv ? 70 ? vtr12 load transient response (2) *3 *4 ? c ? 160 ? temperature which ldo1, ldo2, constant current circuit, matrix sw and rgb turns off. tdet detection temperature *3 *5 ? c ? 110 ? returning temperature tsd11 return temperature voltage regulator (ldo2) output capacitor 1 ? f, output capacitor?s esr less than 0.1 ? voltage regulator (ldo1) output capacitor 1 ? f, output capacitor?s esr less than 0.1 ? electrical characteristics (continued) vb = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. note) *2 : rise time and fall time are defined as below. actual evaluation result of rise time : ldo1 : 290 to 400 ? s, ldo2 : 220 to 310 ? s actual evaluation result of fall time : ldo1 : 6.2 to 8.5 ms, ldo2 : 5.8 to 7.9 ms *3 : typical design value *4 : ldo1, ldo2, constant current circuit, and matrix sw and rgb are turned off when tsd is high. when tsd is high, the register is set as 14hd1 = 1. however, data can be read only when the register is read immediately after int occurs since internal regulator is turned off. *5 : only ldo1 and ldo2 return after on state of tsd. a logic part will be in reset state. ldocnt serial ldo2 10% 90% tsu2 tsd2 ldo1 90% 10% tsu1 tsd1 d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 12 of 64 product standards max typ note unit limits condition symbol parameter min microcomputer interface characteristic (vdd = 1.85 v ? 3 %) read access timing *3 ns ? 125 ? ? tscyc1 clk cycle time *3 ns ? 60 ? ? twhc1 clk cycle time high period *3 ns ? 60 ? ? twlc1 clk cycle time low period *3 ns ? 62 ? ? tss1 serial-data setup time *3 ns ? 62 ? ? tsh1 serial-data hold time *3 ns ? 62 ? ? tcsw1 transceiver interval *3 ns ? 5 ? ? tcss1 chip enable setup time *3 ns ? 5 ? ? tcgh1 chip enable hold time *3 ns ? 25 ? only read mode tdodly1 dc delay time *3 ns ? 60 ? ? twlc1 clk cycle time low period *3 ns ? 5 ? ? tcgh1 chip enable hold time *3 ns ? 62 ? ? tsh1 serial-data hold time *3 ns ? 62 ? ? tcsw1 transceiver interval *3 ns ? 5 ? ? tcss1 chip enable setup time *3 ns ? 62 ? ? tss1 serial-data setup time microcomputer interface characteristic (vdd = 1.85 v ? 3 %) write access timing *3 ns ? 125 ? ? tscyc1 clk cycle time *3 ns ? 60 ? ? twhc1 clk cycle time high period twlc1 clk do di timing chart tscyc1 tsh1 tss1 ce tcss1 tcsw1 tcgh1 tdodly1 twhc1 electrical characteristics (continued) vb = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. note) *3 : typical design value d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 13 of 64 product standards pin configuration top view 34 35 36 37 38 39 40 41 42 43 44 r rgbgnd g b do di clk ce int ldo2 n.c. 22 21 20 19 18 17 16 15 14 13 12 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 n.c. ledctl y0 y1 vled1 y2 y3 y4 y5 vled2 n.c. n.c. n.c. x6 x5 x4 pgnd x3 x2 x1 x0 n.c. n.c. vb ldo1 rstb iref ldocnt vrefd agnd y6 n.c. n.c. d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 14 of 64 product standards pin functions no connection ? n.c. 1 10 11 12 22 23 32 33 44 the power supply's connect terminal for bgr circuit and ldo circuit. power supply vb 2 ldo1 ( 1.85 v ) output terminal. output ldo1 3 reset input terminal ("l" active ) input rstb 4 the resistance connect terminal for constant current value setup. output iref 5 on/off control terminal of ldo1 and ldo2. input ldocnt 6 bgr circuit output terminal. output vrefd 7 the gnd terminal for analog circuitry. ground agnd 8 the output terminal of matrix switching control. it connects with the g column of matrix led. output y6 9 the power supply's connect terminal for matrix led. connect with the output of battery or step-up dc/dc converter power supply vled2 vled1 13 18 the output terminal of matrix switching control. it connects with the f column of matrix led. output y5 14 the output terminal of matrix switching control. it connects with the e column of matrix led. output y4 15 the output terminal of matrix switching control. it connects with the d column of matrix led. output y3 16 the output terminal of matrix switching control. it connects with the c column of matrix led. output y2 17 the output terminal of matrix switching control. it connects with the b column of matrix led. output y1 19 the output terminal of matrix switching control. it connects with the a column of matrix led. output y0 20 led's lighting on/off control terminal. ( it is based on register 0ah.) input ledctl 21 description type pin name pin no. d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 15 of 64 product standards pin functions (continued) constant current circuit. the output terminal of pwm control. it connects with the 1st row of matrix led. output x0 24 constant current circuit. the output terminal of pwm control. it connects with the 2nd row of matrix led. output x1 25 constant current circuit. the output terminal of pwm control. it connects with the 3rd row of matrix led. output x2 26 constant current circuit. the output terminal of pwm control. it connects with the 4th row of matrix led. output x3 27 the gnd terminal for matrix led ground pgnd 28 constant current circuit. the output terminal of pwm control. it connects with the 5th row of matrix led. output x4 29 constant current circuit. the output terminal of pwm control. it connects with the 6th row of matrix led. output x5 30 constant current circuit. the output terminal of pwm control. it connects with the 7th row of matrix led. output x6 31 led contact terminal. output r 34 the gnd terminal for rgb terminal. ground rgbgnd 35 led contact terminal. output g 36 led contact terminal. output b 37 data output terminal for spi interface. output do 38 data input terminal for spi interface. input di 39 clock input terminal for spi interface. input clk 40 chip-enable terminal for spi1 interface. ("h" active ) input ce 41 interrupt output terminal. output int 42 ldo2 ( 2.85 v ) output terminal. output ldo2 43 description type pin name pin no. d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 16 of 64 product standards fixed pattern rom command decoding spi rgb color unit control 11 10 9 8 7 6 5 4 3 2 vb ldo1 rstb iref ldocnt vrefd agnd y6 22 21 20 19 18 17 16 15 14 13 12 y5 y4 y3 y2 vled1 y1 y0 ledctl xo x1 x2 x3 pgnd x4 x5 x6 44 43 42 41 40 39 38 37 36 35 34 rgbgnd g b do di clk ce int ldo2 r vled2 iref htsd on/off level shift pattern register ram register 1 on/off standby on/off 33 constant current control (7-ch) pwm control (7-ch) 32 31 30 29 28 27 26 25 24 23 1 on/off n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. ldo2 2.85 v/30 ma scan switch (7-ch) level shift bgr tsd ldo1 1.85 v/30 ma functional block diagram notes: this block diagram is for explaining functions. part of the block diagram may be omitted, or it may be simplified. d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 17 of 64 product standards normal mode standby mode normal mode off off normal mode off mode ? the signal from serial interface is not received in ldocnt = low and the state of reg28 = low or reg18 = low. ? it shifts to standby mode with ldocnt = low and reg28 = high. ? the signal from serial interface is not received at standby-mode. (power supply for logic is ldo1 and ldo2.) therefore, standby release by the signal from serial interface cannot be performed. ? in standby-mode, if ldocnt is switched to high from low, it will return to the normal mode. ? it cannot shift to off-mode from standby-mode. once returning to the normal mode, please shift to off-mode. 0/1 0/1 "l" "h" 1 0 0 0/1 0 reg28 ? regardless of the value of reg18, ldo1 turns on at ldocnt = high. ? regardless of the value of reg28, ldo2 turns on at ldocnt = high. ? serial interface signal is not received at rstb = low ? 5 ms after being set to ldocnt = high, the receptionist of serial interface signal is attained. ? rstb terminal prohibits the input signal of those other than a rectangle wave. ? all register setting become default setting if rstb = low ? (the default setting of reg18 and reg28 are [1] ? if rstb = low before ldocnt = low, ldo1 and ldo2 can?t turn off. ) ? all register setting become default setting when ldo2 turn off. ? the setting order to change off mode is as following. ? reg18, 28 = [0] ldocnt = "l" rstb = "l" 0 "h" "l" 0/1 "h" ? it is necessary to make it ldocnt = high for the return from off-mode. 0 low note reg18 ldocnt operation 1. explanation in each mode (power supply starting sequence) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 18 of 64 product standards * it is a waveform in the case of applying reset to register setup at standby mode. * maintain the state of rstb = high to hold the register setup. ? shift to the normal mode from standby mode low power mode ldocnt ldo1 ldo2 a register input is possible. over 5 ms rstb* over 3 ms reg18 [address : 02h] reg28 [address : 02h] ldocnt ldo1 ldo2 reg18 [address : 02h] reg28 [address : 02h] a register input is possible. over 5 ms rstb over 3 ms ? shift to the norma l mode from off-mode operation (continued) 1. explanation in each mode (power supply starting sequence) (continued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 19 of 64 product standards ldocnt ldo1 ldo2 set reg18 and reg28 to low before ldocnt. over 1 ms reg18 [address : 02h] reg28 [address : 02h] rstb a register input is possible. over 3ms ? shift to the off-mode from normal mode low power mode set reg18 to low before ldocnt. ldocnt ldo1 ldo2 a register input is possible. over 1 ms reg18 [address : 02h] reg28 [address : 02h] rstb ? shift to the standby mode from normal mode operation (continued) 1. explanation in each mode (power supply starting sequence) (continued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 20 of 64 product standards "h" "h" "l" "l" vbat prohibition "h" on "h" off "l" off "l" mode ldocnt note) "l" in column of vbat and ldocnt means 0 v, "h" means 3.1 to 4.6 v ( operating supply voltage range ). ? logic pin condition note)*: logic state for pins indicated as ?output? under pin state shows the output level. logic state for pins indicated as ?input? under pin state shows the input level to be set to the pins. depends on each mode input ldocnt "l" input ledctl "l" output do "l" input di "l" input clk "l" input ce "l" output int logic* pin state pin name the following setting is common for off, standby and normal mode. the pin setting when rstb = low, under normal mode is as follows. ? shift to the off-mode from normal mode operation (continued) 1. explanation in each mode (power supply starting sequence) (continued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 21 of 64 product standards ? the following waveform is an internal signal. in following yx = xx = low, the waveform of actual yx terminal is set to hi-z. ? it is controlled by internal 1.2 mhz clock in default condition. ? y side switches from y0 to y6 in that order. the turning on term of each pin is constant 945clock (787.5 ? s) and each turning on term includes 8clock (6.67 ? s) interval. ? "*" mark shows the turning on term and d3, d6 is the turning off term in the following figure. ?7 ? 7 matrix display is controlled by x0 to x6 with yx switching timing. y0 y1 y2 y3 y5 x0 to x6 y4 y6 6671clk (about 180.83 hz) 8clk (6.67 ? s) 945clk (787.5 ? s) pwm minimum width 63clk (52.5 ? s) * * * * * * d0 d1 d2 d3 d4 d5 d6 d0 ? matrix part operation waveform operation (continued) 2. explanation of operation d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 22 of 64 product standards all the logic portions to which the power supply is not connected are connected to vb as power supplies. reg28 bgr vbatt tsd ldocnt vb ce clk di do level shift register rst rstb ldo2 2.85 v 1 ? f 1 ? f ldo2 ldo1 ldo1 1.85 v reg18 level shift on/off on/off standby on/off htsd on/off 1 ? f vrefd level shift ldo1 ldo2 ldo1 ldo2 ldo2 vb ldo2 ? reset part block configuration operation (continued) 3. block configuration d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 23 of 64 product standards a b c d efg 1 2 3 4 5 6 7 y0 y1 y2 y3 y4 y5 y6 x0 x1 x2 x3 x4 x5 x6 the connected terminal name led?s number led?s number ? led matrix driver circuit can display character and pattern by controlling the 7 ? 7 matrix led individually. ? in this specification, led?s number controlled by each terminal can be matched off against the following figure. ? it is controlled by internal 1.2 mhz clock in default condition. ? in the scroll mode, led matrix can move the display of character from right to left as the following arrangement. ? explanation of matrix led part, matrix led?s number operation (continued) 3. block configuration (continued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 24 of 64 product standards x0 ldo2 iref control logic dac bgr v(iref) = 0.54 v r(iref) = 27 k ? 20 ? a vled ibl1 panasonic erj2rhd273x q1 q2 1.24 v vb 245 k ? 187 k ? x0 terminal case ? the reference current for constant current driver is calculated by the following formula. v(iref) / r(iref) = 0.54 v / 27 k ? = 20 ? a ? the led driver current can be set from 0 ma to 30 ma by register setting via serial interface. ? the constant current value can be changed by the external resistor value of iref terminal, but the accuracy in case of that setting is not guaranteed. ? erj2rhd273x is recommended for the external resistor of iref terminal to keep the constant current accuracy. ? equivalent circuit of matrix led driver operation (continued) 3. block configuration (continued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 25 of 64 product standards ? register map operation (continued) 4. register and address for test ? ? tsd cpuwrer frmint ram act ? ? ? facgd1 iofactor r 14h ? disrgb dismtx ? ? ? ? ledact ledctl w 0ah w/r for test for test for test for test for test for test for test for test for test for test for test for test for test for test for test w w r/w ? ? ? 08h 18h 17h 16h 15h ? ? ? ? intvsel vddsel 1ah 19h 10h 09h 07h 06h 05h 04h 03h data name sub address 13h 12h 11h reg28 reg18 ? ? ? ? ? ? ldocnt 02h ? ? oscen ? ? ? powercnt 01h d5 d6 d7 data d0 d1 d2 d3 d4 d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 26 of 64 product standards * access the address from 6bh to 77h is prohibited. for test 6bh for test 6dh for test 6fh for test 2eh ramnum ? rgbon ? ? ? ? ? ? ? rgbon r/w 2ch rgbdata[5:0] ? ? rgbdata r/w 2dh ? for test 2bh settime[1:0] ? ? ? ? ? ? settime r/w 28h repon ? ? ? ? setto[7:0] setto r/w 26h sclon ? ? ? ? ? ? scroll r/w 2ah for test 75h for test 70h for test 71h for test 72h for test 73h for test 74h for test 76h ram2 ram1 ? ? ? ? ? ? ramrst r/w 29h ? ? ? ? ? ? ramnum r/w 30h for test r/w r/w r/w r/w r/w r/w r/w r/w 77h ? ? ? ? ? ? setfrom[7:0] setfrom 25h ? ? repon 27h copystart selram ? ? ramcopy 24h selrom[7:0] romsel 23h rom77[1:0] ? ? ? ? ? ffrom 22h data name sub address mtxdata[7:0] mtxdata 21h mtxon ? ? ? ? ? ? ? mtxon 20h d5 d6 d7 data d0 d1 d2 d3 d4 ? register map (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 27 of 64 product standards dla1[1:0] fra1[1:0] bla1[3:0] a1 31h dla2[1:0] fra2[1:0] bla2[3:0] a2 32h dla3[1:0] fra3[1:0] bla3[3:0] a3 33h dla4[1:0] fra4[1:0] bla4[3:0] a4 34h dla5[1:0] fra5[1:0] bla5[3:0] a5 35h dla6[1:0] fra6[1:0] bla6[3:0] a6 36h dla7[1:0] fra7[1:0] bla7[3:0] a7 37h dlb1[1:0] frb1[1:0] blb1[3:0] b1 38h dlb2[1:0] frb2[1:0] blb2[3:0] b2 39h dlb3[1:0] frb3[1:0] blb3[3:0] b3 3ah dlb4[1:0] frb4[1:0] blb4[3:0] b4 3bh dlb5[1:0] frb5[1:0] blb5[3:0] b5 3ch dlb6[1:0] frb6[1:0] blb6[3:0] b6 3dh dlb7[1:0] frb7[1:0] blb7[3:0] b7 3eh dlc1[1:0] frc1[1:0] blc1[3:0] c1 3fh dlc2[1:0] frc2[1:0] blc2[3:0] c2 40h dlc3[1:0] frc3[1:0] blc3[3:0] c3 41h dlc4[1:0] frc4[1:0] blc4[3:0] c4 42h dlc5[1:0] frc5[1:0] blc5[3:0] c5 43h dlc6[1:0] frc6[1:0] blc6[3:0] c6 44h dlc7[1:0] frc7[1:0] blc7[3:0] c7 45h dld1[1:0] frd1[1:0] bld1[3:0] d1 46h dld2[1:0] frd2[1:0] bld2[3:0] d2 47h dld3[1:0] frd3[1:0] bld3[3:0] d3 48h dld4[1:0] frd4[1:0] bld4[3:0] d4 49h dld5[1:0] frd5[1:0] bld5[3:0] d5 4ah dld6[1:0] frd6[1:0] bld6[3:0] d6 4bh dld7[1:0] frd7[1:0] bld7[3:0] d7 4ch data name sub address d5 d6 d7 data d0 d1 d2 d3 d4 operation (continued) 4. register and address (c ontinued) ram address map d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 28 of 64 product standards dlg7[1:0] frg7[1:0] blg7[3:0] g7 61h dlledb[1:0] dlledg[1:0] dlledr[1:0] frledb[1:0] frledg[1:0] frledr[1:0] blledr[3:0] ledr 62h blledg[3:0] ledg 63h blledb[3:0] ledb 64h dle1[1:0] fre1[1:0] ble1[3:0] e1 4dh dle2[1:0] fre2[1:0] ble2[3:0] e2 4eh dle3[1:0] fre3[1:0] ble3[3:0] e3 4fh dle4[1:0] fre4[1:0] ble4[3:0] e4 50h dle5[1:0] fre5[1:0] ble5[3:0] e5 51h dle6[1:0] fre6[1:0] ble6[3:0] e6 52h dle7[1:0] fre7[1:0] ble7[3:0] e7 53h dlf1[1:0] frf1[1:0] blf1[3:0] f1 54h dlf2[1:0] frf2[1:0] blf2[3:0] f2 55h dlf3[1:0] frf3[1:0] blf3[3:0] f3 56h dlf4[1:0] frf4[1:0] blf4[3:0] f4 57h dlf5[1:0] frf5[1:0] blf5[3:0] f5 58h dlf6[1:0] frf6[1:0] blf6[3:0] f6 59h dlf7[1:0] frf7[1:0] blf7[3:0] f7 5ah dlg1[1:0] frg1[1:0] blg1[3:0] g1 5bh dlg2[1:0] frg2[1:0] blg2[3:0] g2 5ch dlg3[1:0] frg3[1:0] blg3[3:0] g3 5dh dlg4[1:0] frg4[1:0] blg4[3:0] g4 5eh dlg5[1:0] frg5[1:0] blg5[3:0] g5 5fh dlg6[1:0] frg6[1:0] blg6[3:0] g6 60h data name sub address d5 d6 d7 data d0 d1 d2 d3 d4 operation (continued) 4. register and address (c ontinued) ram address map (continued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 29 of 64 product standards display contents of the pattern pattern no. t alphabetic character 30 s alphabetic character 29 nothing all putting out lights 0 r alphabetic character 28 q alphabetic character 27 p alphabetic character 26 o alphabetic character 25 n alphabetic character 24 m alphabetic character 23 l alphabetic character 22 k alphabetic character 21 j alphabetic character 20 i alphabetic character 19 h alphabetic character 18 g alphabetic character 17 f alphabetic character 16 e alphabetic character 15 d alphabetic character 14 c alphabetic character 13 b alphabetic character 12 a alphabetic character 11 9 number 10 8 number 9 7 number 8 6 number 7 5 number 6 4 number 5 3 number 4 2 number 3 1 number 2 0 number 1 [00000000] - [10010101] : rom(only luminosity) 7 ? 7 pattern no.0 (default) to pattern no.149 display contents of the pattern pattern no. w alphabetic character 59 x alphabetic character 60 y alphabetic character 61 v alphabetic character 58 u alphabetic character 57 t alphabetic character 56 s alphabetic character 55 r alphabetic character 54 q alphabetic character 53 p alphabetic character 52 o alphabetic character 51 n alphabetic character 50 m alphabetic character 49 l alphabetic character 48 k alphabetic character 47 j alphabetic character 46 i alphabetic character 45 h alphabetic character 44 g alphabetic character 43 f alphabetic character 42 e alphabetic character 41 d alphabetic character 40 c alphabetic character 39 b alphabetic character 38 a alphabetic character 37 z alphabetic character 36 y alphabetic character 35 x alphabetic character 34 w alphabetic character 33 v alphabetic character 32 u alphabetic character 31 ? rom address map operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 30 of 64 product standards display contents of the pattern pattern no. 29 number 92 28 number 91 z alphabetic character 62 27 number 90 26 number 89 25 number 88 24 number 87 23 number 86 22 number 85 21 number 84 20 number 83 19 number 82 18 number 81 17 number 80 16 number 79 15 number 78 14 number 77 13 number 76 12 number 75 11 number 74 10 number 73 09 number 72 08 number 71 07 number 70 06 number 69 05 number 68 04 number 67 03 number 66 02 number 65 01 number 64 00 number 63 display contents of the pattern pattern no. 58 number 121 59 number 122 60 number 123 57 number 120 56 number 119 55 number 118 54 number 117 53 number 116 52 number 115 51 number 114 50 number 113 49 number 112 48 number 111 47 number 110 46 number 109 45 number 108 44 number 107 43 number 106 42 number 105 41 number 104 40 number 103 39 number 102 38 number 101 37 number 100 36 number 99 35 number 98 34 number 97 33 number 96 32 number 95 31 number 94 30 number 93 [00000000] - [10010101] : rom(only luminosity) 7 ? 7 pattern no.0 (defaul t) to pattern no.149 ? rom address map (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 31 of 64 product standards display contents of the pattern pattern no. symbol 144 symbol 145 symbol 146 symbol 147 symbol 148 symbol 149 display contents of the pattern pattern no. zero antenna symbol 124 symbol 143 / symbol 142 - symbol 141 + symbol 140 symbol 139 symbol 138 symbol 137 symbol 136 ? symbol 135 ! symbol 134 : symbol 133 << symbol 132 >> symbol 131 || symbol 130 ? symbol 129 symbol 128 three antenna symbol 127 two antenna symbol 126 one antenna symbol 125 [00000000] - [10010101] : rom(only luminosity) 7 u 7 pattern no.0 (defaul t) to pattern no.149 ? rom address map (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 32 of 64 product standards [10010110] - [11010000] : rom(luminosity + cycle + delay) 7 ? 7 pattern no.150 to pattern no.208 display contents of the pattern pattern no. gradation 150 gradation 158 gradation 157 gradation 156 gradation 155 gradation 154 gradation 153 gradation 152 gradation 151 display contents of the pattern pattern no. gradation 159 gradation 160 gradation 161 gradation 162 gradation 163 gradation 164 gradation 165 gradation 166 gradation 167 ? rom address map (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 33 of 64 product standards display contents of the pattern pattern no. gradation 177 gradation 178 gradation 179 gradation 180 gradation 181 gradation 182 gradation 183 gradation 184 gradation 185 [10010110] - [11010000] : rom(luminosity + cycle + delay) 7 ? 7 pattern no.150 to pattern no.208 display contents of the pattern pattern no. gradation 168 gradation 176 gradation 175 gradation 174 gradation 173 gradation 172 gradation 171 gradation 170 gradation 169 ? rom address map (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 34 of 64 product standards display contents of the pattern pattern no. gradation 195 gradation 196 gradation 197 gradation 198 gradation 199 gradation 200 gradation 201 gradation 202 gradation 203 [10010110] - [11010000] : rom(luminosity + cycle + delay) 7 ? 7 pattern no.150 to pattern no.208 display contents of the pattern pattern no. gradation 186 gradation 194 gradation 193 gradation 192 gradation 191 gradation 190 gradation 189 gradation 188 gradation 187 ? rom address map (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 35 of 64 product standards [10010110] - [11010000] : rom(luminosity + cycle + delay) 7 ? 7 pattern no.150 to pattern no.208 display contents of the pattern pattern no. gradation 204 gradation 208 gradation 207 gradation 206 gradation 205 ? rom address map (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 36 of 64 product standards ramnum ? ? ? ? ? ? ? ramnum r/w 30h rgbdata[5:0] ? ? rgbdata r/w 2dh rgbon ? ? ? ? ? ? ? rgbon r/w 2ch scltime[1:0] ? ? ? ? ? ? scltime r/w 2bh sclon ? ? ? ? ? ? ? scroll r/w 2ah ram2 ram1 ? ? ? ? ? ? ramrst r/w 29h settime[1:0] ? ? ? ? ? ? settime r/w 28h repon ? ? ? ? ? ? ? repon r/w 27h setto[7:0] setto r/w 26h setfrom[7:0] setfrom r/w 25h copy start selram ? ? ? ? ? ? ramcopy r/w 24h selrom[7:0] romsel r/w 23h rom77[1:0] ? ? ? ? ? ? ffrom r/w 22h mtxdata[7:0] mtxdata r/w 21h tsd cpu wrer frmint ram act ? ? ? facg d1 iofactor r 14h ? ? mtxon ? ? ? ? ? ? ? mtxon r/w 20h w r/w data name sub address ? ? oscen ? ? ? powercnt 01h d5 d6 d7 data d0 d1 d2 d3 d4 about the following addresses, even if an internal clock or an external clock does not exist, read / write is possible in the data to register. ho wever, it cannot be given to operation finally needed. ? register table which needs a clock operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 37 of 64 product standards dla1[1:0] fra1[1:0] bla1[3:0] a1 31h dla2[1:0] fra2[1:0] bla2[3:0] a2 32h dla3[1:0] fra3[1:0] bla3[3:0] a3 33h dla4[1:0] fra4[1:0] bla4[3:0] a4 34h dla5[1:0] fra5[1:0] bla5[3:0] a5 35h dla6[1:0] fra6[1:0] bla6[3:0] a6 36h dla7[1:0] fra7[1:0] bla7[3:0] a7 37h dlb1[1:0] frb1[1:0] blb1[3:0] b1 38h dlb2[1:0] frb2[1:0] blb2[3:0] b2 39h dlb3[1:0] frb3[1:0] blb3[3:0] b3 3ah dlb4[1:0] frb4[1:0] blb4[3:0] b4 3bh dlb5[1:0] frb5[1:0] blb5[3:0] b5 3ch dlb6[1:0] frb6[1:0] blb6[3:0] b6 3dh dlb7[1:0] frb7[1:0] blb7[3:0] b7 3eh dlc1[1:0] frc1[1:0] blc1[3:0] c1 3fh dlc2[1:0] frc2[1:0] blc2[3:0] c2 40h dlc3[1:0] frc3[1:0] blc3[3:0] c3 41h dlc4[1:0] frc4[1:0] blc4[3:0] c4 42h dlc5[1:0] frc5[1:0] blc5[3:0] c5 43h dlc6[1:0] frc6[1:0] blc6[3:0] c6 44h dlc7[1:0] frc7[1:0] blc7[3:0] c7 45h dld1[1:0] frd1[1:0] bld1[3:0] d1 46h dld2[1:0] frd2[1:0] bld2[3:0] d2 47h dld3[1:0] frd3[1:0] bld3[3:0] d3 48h dld4[1:0] frd4[1:0] bld4[3:0] d4 49h dld5[1:0] frd5[1:0] bld5[3:0] d5 4ah dld6[1:0] frd6[1:0] bld6[3:0] d6 4bh dld7[1:0] frd7[1:0] bld7[3:0] d7 4ch data name sub address d5 d6 d7 data d0 d1 d2 d3 d4 about the following addresses, when an internal clock or an external clock does not exist, data cannot be read / write in at register. ? register table which needs a clock (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 38 of 64 product standards dlg7[1:0] frg7[1:0] blg7[3:0] g7 61h dlledb[1:0] dlledg[1:0] dlledr[1:0] frledb[1:0] frledg[1:0] frledr[1:0] blledr[3:0] ledr 62h blledg[3:0] ledg 63h blledb[3:0] ledb 64h dle1[1:0] fre1[1:0] ble1[3:0] e1 4dh dle2[1:0] fre2[1:0] ble2[3:0] e2 4eh dle3[1:0] fre3[1:0] ble3[3:0] e3 4fh dle4[1:0] fre4[1:0] ble4[3:0] e4 50h dle5[1:0] fre5[1:0] ble5[3:0] e5 51h dle6[1:0] fre6[1:0] ble6[3:0] e6 52h dle7[1:0] fre7[1:0] ble7[3:0] e7 53h dlf1[1:0] frf1[1:0] blf1[3:0] f1 54h dlf2[1:0] frf2[1:0] blf2[3:0] f2 55h dlf3[1:0] frf3[1:0] blf3[3:0] f3 56h dlf4[1:0] frf4[1:0] blf4[3:0] f4 57h dlf5[1:0] frf5[1:0] blf5[3:0] f5 58h dlf6[1:0] frf6[1:0] blf6[3:0] f6 59h dlf7[1:0] frf7[1:0] blf7[3:0] f7 5ah dlg1[1:0] frg1[1:0] blg1[3:0] g1 5bh dlg2[1:0] frg2[1:0] blg2[3:0] g2 5ch dlg3[1:0] frg3[1:0] blg3[3:0] g3 5dh dlg4[1:0] frg4[1:0] blg4[3:0] g4 5eh dlg5[1:0] frg5[1:0] blg5[3:0] g5 5fh dlg6[1:0] frg6[1:0] blg6[3:0] g6 60h data name sub address d5 d6 d7 data d0 d1 d2 d3 d4 about the following addresses, when an internal clock or an external clock does not exist, data cannot be read / write in at register. ? register table which needs a clock (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 39 of 64 product standards ? ?? oscen ? default ? ? ? data name 01h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 d2 : oscen on/off bit fo r internal oscillators [0] : internal oscillating circuit is off (default) [1] : internal oscillating circuit is on ? the variation width of an internal oscillator is set to 0.96mhz - 1.44 mhz. ? the variation width of an internal clock is set to 694.4 ns - 1042 ns. reg28 ? ? ? ? default reg18 ? ? data name 02h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 1 1 0 0 0 d0 d1 d2 d3 d4 d1 : reg18 the on/off control for ldo1(when ldocnt terminal is low) [0] : ldo1 off [1] : ldo1 on (default) d0 : reg28 the on/off control for ldo2( when ldocnt terminal is low ) [0] : ldo2 off [1] : ldo2 on (default) ? when ldocnt terminal is high, regardless of the state of reg18, ldo1 will be activated. ? when ldocnt terminal is high, regardless of the state of reg28, ldo2 will be activated. ? set ldocnt to low afte r setting reg28 to low to put into off mode. ? register map detailed explanation operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 40 of 64 product standards default for test data name 03h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 default for test data name 04h r 0 d5 r 0 d6 r 0 d7 data mode sub address r r r r r 0 0 0 0 0 d0 d1 d2 d3 d4 default for test data name 05h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 default for test data name 06h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 default for test data name 07h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 *don?t access to address from 03h to 07h. ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 41 of 64 product standards default for test data name 08h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 *don?t access to address from 08h to 09h. default for test data name 09h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 ? disrgb dismtx ? ? ? ? default ledact data name 0ah w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 d7 : ledact a putting-out-lights setup of led by ledctl terminal. [0] : the light is switched on at ledctl = low(default) [1] : the light is switched on at ledctl = high d2 : dismtx a putting-out-lights on/off setup of 7 ? 7 dots matrix led by ledctl terminal. [0] : putting-out-lights control off by ledctl terminal. (default) [1] : putting-out-lights control on by ledctl terminal. d1 : disrgb a putting-out-lights on/off setup of r, g and b terminal by ledctl terminal. [0] : putting-out-lights control off by ledctl terminal. (default) [1] : putting-out-lights control on by ledctl terminal. ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 42 of 64 product standards default for test data name 10h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 default for test data name 11h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 for test default data name 12h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 default for test data name 13h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 *don?t access to address from 10h to 13h. ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 43 of 64 product standards tsd cpuwrer frmint ramact ? ? ? default facgd1 data name 14h r 0 d5 r 0 d6 r 0 d7 data mode sub address r r r r r 0 0 0 0 0 d0 d1 d2 d3 d4 d7 : facgd1 [0] : normal operation (default) [1] : no read clearance d3 : ramact internal ram access judgment [0] : ram is not accessed. (default) [1] : ram is accessed. d2 : frmint frame display end judgment during scroll display [0] : under frame display (default) [1] : frame display end d1 : cpuwrer cpu access error judgment [0] : cpu access error does not occur. (default) [1] : cpu access error occurs. d0 : tsd abnormal detection of tsd error [0] : tsd abnormal detection does not occur. (default) [1] : tsd abnormal detection occurs. ? cpuwrer indicates the error when cpu writes the data to 31h to 64h during copying from rom to ram1 or ram2. ? the write contents from cpu are not reflected in this lsi at cpuwrer = high. write from cpu again. ? the interval of facgd1 = "1" is maximum 1.93 ? s (at the internal clock operation) from the renewal time of data. ? at facgd1 = "1", if address 14h data is read, data of d0 to d6 are cleared. ? ram access from cpu cannot be performed at ramact = "1" . ? when each address 14h register is set to high, t he pulse in a cycle of 4 ms is output from int. ? the pulse output from int continues an output until address 14h is read. ? rstb terminal = low can reset to stop the int pulse signal in case of that the serial read function is not used. ? the states for ramact = "1" are shown below. 1. while copying to ram from rom. 2. while clearing ram ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 44 of 64 product standards default for test data name 15h r 0 d5 r 0 d6 r 0 d7 data mode sub address r r r r r 0 0 0 0 0 d0 d1 d2 d3 d4 default for test data name 16h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 default for test data name 17h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 default for test data name 18h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 default for test data name 19h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 *don?t access to address from 15h to 19h. ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 45 of 64 product standards ? ? ?? ? ? ? default intvsel data name 1ah w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7 : intvsel the voltage setup of int terminal [0] : 1.85 v (default) [1] : 2.85 v ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 46 of 64 product standards mtxon ? ? ? ? ? ? default ? data name 20h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d0 : mtxon on/off setup of matrix led [0] : off (default) [1] : on ? during mtxon = "1", subsequent rom, ram, and the control contents to a register are sequentially processed and lit up. ? wait 5 ms when mtxon is set to "1" after address 01h oscen is set to "1". ? set mtxon to "1", and then set up other addresses to display the matrix part. default mtxdata[7:0] data name 21h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-0 : mtxdata[7:0] address setup of rom/ram of the data to read [00000000] - [10010101] : rom ( only luminosity ) 7 ? 7 pattern no.0 (d efault) to no.149 [10010110] - [11010000] : rom ( luminosity + cycle + delay ) 7 ? 7 pattern no. 150 to no.208 [11010001] : ram ( luminosity + cycle + delay ) 7 ? 7 pattern ram no.1 [11010010] : ram ( luminosity + cycle + delay ) 7 ? 7 pattern ram no.2 ? the pattern no.0 of rom is all "0" data of matrix led. ? accessing to 21h is disabled while copying from rom to ram (copystart 24h = "1"). ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 47 of 64 product standards ? rom77[1:0] ? ? ? ? default ? data name 22h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d1-0 : rom77[1:0] lighting control of the 7 ? 7 (led no.a1-g7) fixed pattern of rom [00] : rom data is displayed. [01] : rom data is displayed by firefly lighting in 1 s. [10] : rom data is displayed by firefly lighting in 2 s. [11] : rom data is displayed by firefly lighting in 3 s ? during display of repetition (repon = "1"), rom77 must not be changed. a b c d efg 1 2 3 4 5 6 7 t t1 t3 t2 t4 t1 = t2 = t4 = 249.2 ms t3 = 265.8 ms the peak value of luminosity is a value set up by rom. luminosity firefly lighting cycle : t led?s number led?s number ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 48 of 64 product standards default selrom[7:0] data name 23h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-0 : selrom[7:0] address setup of rom copied to ram [00000000] - [10010101] : rom (only luminosity) 7 ? 7 pattern no.0 (default) to no.149 [10010110] - [11010000] : rom (luminosity + cycle + delay) 7 ? 7 pattern no.150 to no.208 ? accessing to 23h is disabled while copying from rom to ram (copystart 24h = "1"). ? ?? ? selram copystart ? default ? data name 24h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d1 : selram ram number setup of a copy place. [0] : ram no.1 [1] : ram no.2 d0 : copystart copy start on/off control to ram from rom [0] : off [1] : the copy set up by selrom and selram is started. (it returns to 0 by internal 51 clk.) ? address 24h is only for copying data to ram and never start led display. (however, if this ram is copied when led display is showing, led display is updated.) ? writing in address 21h-mtxdata, 2ah-sclon, and 27h-repon is dis abled while copying. (ramact flag is raised.) ? accessing to selram is disabled while copying from rom to ram (copystart 24h = "1") ? don?t write address 29h (ram-clear ) while copying. (the waiting time for over 1 ms is required after copystart.) ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 49 of 64 product standards default setfrom[7:0] data name 25h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-0 : setfrom[7:0] an address setup of the rom frame data at the repetition display start. [00000000] - [10010101] : rom (only luminosity) 7 ? 7 pattern no.0 (default) to no.149 [10010110] - [11010000] : rom (luminosity + cycle + delay) 7 ? 7 pattern no.150 to no.208 ? during display of repetition (repon = "1"), don?t change the setting of setfrom. default setto[7:0] data name 26h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-0 : setto[7:0] address setup of the rom frame data at the repetition display end [00000000] - [10010101] : rom (only luminosity) 7 ? 7 pattern no.0 (default) to no.149 [10010110] - [11010000] : rom (luminosity + cycle + delay) 7 ? 7 pattern no.150 to no.208 ? during display of repetition (repon = "1"), don?t change the setting of setto. ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 50 of 64 product standards repon ? ? ? ? ? ? default ? data name 27h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d0 : repon repetition display on/off control [0] : repetition display off (default) [1] : repetition display on ? during display of repetition, display of set-up rom is continued. ? a repetition display is started in the state of mtxon = "1" and repon = "1". ? accessing to 27h is disabled while copying from rom to ram (copystart 24h = "1"). ? when the setting of sclon is changed from low to high while repon = "1", repon becomes "0" and it shifts to scroll function. ? during display of repetition (repon = "1"), don?t change the setting of setfrom and setto. settime[1:0] ? ? ? ? ? default ? data name 28h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d1-0 : settime[1:0] a frame display time setup of repetition display [00] : 1 s (default) [01] : 2 s [10] : 3 s [11] : 4 s ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 51 of 64 product standards ram2 ram1 ? ? ? ? ? default ? data name 29h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d1 : ram1 the data in 7 ? 7 ram1 is cleared. 0 : overwrite is possible. (default) 1 : the data in 7 ? 7 ram1 is cleared. (it returns to 0 by internal 2 clk.) d0 : ram2 the data in 7 ? 7 ram2 is cleared. 0 : overwrite is possible. (default) 1 : the data in 7 ? 7 ram2 is cleared. (it returns to 0 by internal 2 clk.) ? don?t set the ram-clear operation for ram1 or ram2 during display of repetition (sclon = "1"). ? don?t set the ram-clear operation (29h) during the copy operation (24h). (the waiting time for over 1 ms is required after copystart.) ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 52 of 64 product standards ? ?sclon ? ? ? ? default ? data name 2ah w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d0 : sclon on/off setup of scroll display [0] : off (default) [1] : on ? the scroll display displays the data which exists in the ram no.1-2 of 7 ? 7 in order of a-g column. the display travel time of a column is the preset value of scltime. ? during display of scroll, data can be written to ram without specifying ram number. (writing is performed to empty ram.) ? the scroll display is started in the state of mtxon = "1" and sclon. ? accessing to 2ah is disabled while copying from rom to ram (copystart 24h = "1"). ? when the setting of repon is changed from "0" to "1" while sclon = "1", sclon becomes "0" and it shifts to repetition display function. ? during display of scroll (sclon = "1"), don?t change the setting of ram1 and ram2. ? once the scroll function was set, then the sclon = "0" or mtxon = "0", rstb terminal must be "l" to reset before the scroll function is set again. scltime[1:0] ?? ? ? ? default ? data name 2bh w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d1-0 : scltime[1:0] frame display time setup of scroll display [00] : 0.1 s (default) [01] : 0.2 s [10] : 0.4 s [11] : 0.8 s ? the display travel time of the column is the preset value of scltime. ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 53 of 64 product standards ? ? rgbon ? ? ? ? default ? data name 2ch w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d0 : rgbon on/off setup of rgb lighting [0] : off (default) [1] : on ? wait 5 ms when rgbon is set to "1" after address 01h oscen is set to "1". rgbdata[5:0] ? default ? data name 2dh w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-0 : rgbdata[5:0] address setup of rom and register which read rgb data [000000] : register is displayed. [000001] - [101010] : rom (rgb pattern, luminosity + cycle + delay) pattern no.1 to no.42 default for test data name 2eh r 0 d5 r 0 d6 r 0 d7 data mode sub address r r r r r 0 0 0 0 0 d0 d1 d2 d3 d4 *don?t access to address 2eh. ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 54 of 64 product standards ramnum ? ? ? ? ? ? default ? data name 30h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d1-0 : ramnum[1:0] ram number setup at the cpu access (read and write). [0] : ram no.1 [1] : ram no.2 ? accessing to 30h is disabled during display of scroll (2ah sclon = "1"). ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 55 of 64 product standards dla1[1:0] fra1[1:0] default bla1[3:0] data name 31h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-4 : bla1[1:0] luminosity setup of led no.a1 [0000] : 0 ma (default) [0001] : 1 ma [0010] : 2 ma [0011] : 3 ma [0100] : 4 ma [0101] : 5 ma [0110] : 8 ma [0111] : 11 ma [1000] : 15 ma [1001] : 17 ma [1010] : 19 ma [1011] : 21 ma [1100] : 24 ma [1101] : 26 ma [1110] : 28 ma [1111] : 30 ma d3-2 : fra1[1:0] firefly operation and cycle setup of the led no.a1 [00] : lighting mode (default) [01] : firefly lighting cycle 1 s [10] : firefly lighting cycle 2 s [11] : firefly lighting cycle 3 s d1-0 : dla1[1:0] firefly operation delay setup of the led no.a1 [00] : no delay (default) [01] : delay 25% [10] : delay 50% [11] : delay 75% ? the operation is the same as above for the addresses to 61h corresponding to each led number. ? the waiting time for 2 or more internal clocks (2 ? s or more) is required after the data from address 31h to 61h is written in. please input other serial commands after that. a b c d efg led?s number 1 2 3 4 5 6 7 led?s number ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 56 of 64 product standards dlledr[1:0] frledr[1:0] default blledr[3:0] data name 62h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-4 : blledr1[1:0] luminosity setup of r1 terminal [0000] : 0 ma (default) [0001] : 1 ma [0010] : 2 ma : : [1110] : 14 ma [1111] : 15 ma d3-2 : frledr1[1:0] firefly operat ion and cycle setup of r1 terminal [00] : lighting mode (default) [01] : firefly lighting cycle 1 s [10] : firefly lighting cycle 2 s [11] : firefly lighting cycle 3 s d1-0 : dlledr1[1:0] firefly operation delay setup of r1 terminal [00] : no delay (default) [01] : delay 25% [10] : delay 50% [11] : delay 75% ? the operation is the same as above for the addresses to 64h corresponding to g and b terminal. ? the waiting time for 2 or more internal clocks (2 ? s or more) is required after the data from address 62h to 64h is written in. please input other serial commands after that. ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 57 of 64 product standards default for test data name 6bh w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 *address from 6bh onwards are registers for test. don't write into these addresses. ? register map detailed explanation (continued) operation (continued) 4. register and address (c ontinued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 58 of 64 product standards ? the interface with microcomputer consists of 16 bit-serial register (8-bit of command, 8-bit of address), and address decoder and transmitting register (8-bit). ? serial interface consists of four terminals of serial clock terminal (clk), serial-data input terminal (di), serial-data output terminal (do), and chip enable input terminal (ce). (1) write operation ? data is taken into internal shift register by the rising edge of clk. (maximum 13 mhz of frequency of clk can be used) ? serial interface consists of four terminals of serial clock terminal (clk), serial-data input terminal (di), serial- data output terminal (do), and chip enable input terminal (ce). ? data is transmitted at msb first in order of a control register address (8-bit) and control command (8-bit). clk di w d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 ce do 0 write access timing (2) transmission operation ? data is taken into internal shift register by the ri sing edge of clk. (a maximum of 6 mhz of frequency of clk can be used) ? it is not possible to read ram data. ? in high interval of ce, reception of data becomes enable. (active : high) ? data is transmitted at msb first in order of a control register address (8-bit) and control command (max 8-bit). read access timing clk do ce di d0 d1 d2 d3 d4 d5 d6 d7 ra0 a1 a2 a3 a4 a5 a6 0 0 ? spi format operation (continued) 5. serial interface format d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 59 of 64 product standards ldo1 bgr tsd vb ldo2 ldo2 ldo1 logic i/o* bgr tsd vled1 vled2 agnd pgnd rgbgnd osc mtx rgb scan *clk, ce, di, do, ledctl ? power supply distribution diagram operation (continued) 6. signal distribution diagram d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 60 of 64 product standards oscillator 1.2 mhz regmap matrix rgb * matrix, rgb operation pwm control read / write of memory data (rom and ram) 14h ramact, frmint, cpuwrer spi (pad) clk (pad) ce (pad) di (pad) do * serial ? parallel conversion sclk serial ? parallel conversion (input) sclk_n parallel ? serial conversion (output) regclk serial ? parallel conversion output is latched in a standup. sclk sclk_n regclk ? control / clock distribution diagram operation (continued) 6. signal distribution diagram (continued) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 61 of 64 product standards dla1[1:0] fra1[1:0] bla1[3:0] 0 0 0 0 00 0 1 example of initial setting for lighting dla1[1:0] fra1[1:0] bla1[3:0] 0 1 1 1 10 0 1 firefly lighting setup 1 s dla1[1:0] fra1[1:0] bla1[3:0] 0 0 1 1 10 1 1 change to cycle 1 s to 2 s dla1[1:0] fra1[1:0] bla1[3:0] 1 0 1 1 10 1 1 change to delay 0 ? 25 % 30 ma t firefly lighting cycle t2 = 2.0268 s fra1 = [10] a1 dla1 = [01] t5 t6 t7 t8 t5 = t6 = t8 = 498.4 ms t7 = 531.6 ms current value a1 serial on 15 ma t firefly lighting cycle t = 1.0134 s fra1 = [01] a1 current value 30 ma serial on t firefly lighting cycle t2 = 2.0268 s fra1 = [10] a1 current value bla1 = [1000] bla1 = [1111] t 30 ma current value bla1 = [1111] bla1 = [1111] serial on serial on ? example of firefly lighting 1 operation (continued) 7. example of firefly lighting d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 62 of 64 product standards ? example of firefly lighting 2 operation (continued) 7. example of firefly lighting (continued) t luminance firefly lighting cycle t1 = 3.040 2 s fra1 = [11] t1 t3 t2 t4 t1 = t2 = t4 = 747.6 ms t3 = 797.4 ms bla1 a1 t luminance firefly lighting cycle t2 = 2.026 8 s frc5 = [10] blc5 c5 t luminance firefly lighting cycle t3 = 1.013 4 s frf3 = [01] t9 = t10 = t12 = 249.2 ms t11 = 265.8 ms blf3 f3 dlc5 = [01] t5 t6 t7 t8 t5 = t6 = t8 = 498.4 ms t7 = 531.6 ms dlf3 = [10] t9 t10 t11 t12 t luminance firefly lighting cycle t1 = 3.040 2 s fre7 = [11] t1 t3 t2 t4 ble7 e7 dle7 = [11] t1 = t2 = t4 = 747.6 ms t3 = 797.4 ms 1. normally, it is not possible to control data when rgbgnd pin voltage is undefined. therefore, please keep the rgbgnd pin voltage at the lowest voltage. 2. please check the input waveform to the clk pin. when inputting clock into the clk pin, if the input clock is ringing with input voltage between 0.4 v to ldo1 ? 0.8 v (input voltage indefinite range), it will result in serial data not able to be written to or be read out from a register. (it is recommended to smooth the rising and falling edge of the input clock by connecting input capacitance (a capacitor, etc.) to the clk pin.) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 63 of 64 product standards package information ( reference data ) d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
AN32058A page 64 of 64 product standards important notice 1. when using the lsi for new models, verify the safety including the long-term reliability for each product. 2. when the application system is designed by using this lsi, please confirm the notes in this book. please read the notes to descriptions and the usage notes in the book. 3. this lsi is intended to be used for general electronic equipment. consult our sales staff in advance for information on the following applications: special applications in which exceptional quality and reliab ility are required, or if the failure or malfunction of this lsi may directly j eopardize life or harm the human body. any applications other than the standard applications intended. (1) space appliance (such as artificial satellite, and rocket) (2) traffic control equipment (such as for automobile, airplane, train, and ship) (3) medical equipment for life support (4) submarine transponder (5) control equipment for power plant (6) disaster prevention and security device (7) weapon (8) others : applications of which reliability equivalent to (1) to (7) is required our company shall not be held responsible for any damage incurred as a result of or in connection with the lsi being used for any special application, unless our company agrees to the use of such special application. 4. this lsi is neither designed nor intended for use in automotive applications or environments unless the speci fic product is designated by our company as compliant with the iso/ts 16949 requirements. our company shall not be held responsible for any damage incurred by customers or any third party as a result of or in connection with the lsi being used in automotive application, unless our company agrees to such application in this book. 5. please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of control led substances, including without limitation, the eu rohs directive. our company shall not be held responsible for any damage incurred as a result of our lsi being used by our customers, not complying with the applicable laws and regulations. 6. pay attention to the direction of lsi. when mounting it in the wrong direction onto the pcb (printed-circuit-board), it migh t emit smoke or ignite. 7. pay attention in the pcb (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins . in addition, refer to the pin description for the pin configuration. 8. perform visual inspection on the pcb before applying power, otherwise damage might happen due to problems such as solder-bridge between the pins of the semiconductor device. also, perform full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the lsi during transportation. 9. take notice in the use of this product that it might be damaged or occasionally emit smoke when an abnormal state occurs such as output pin-vcc short (power supply fault), output pin-gnd short (ground fault), or output-to-output-pin short (load short). safety measures such as installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission will depend on the current capability of the power supply. 10. the protection circuit is for maintaining safety against abnormal operation. therefore, the protection circuit should not w ork during normal operation. especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily exceeded due to output pin to vcc short (power supply fault), or output pin to gnd short (ground fault), the lsi might be damaged before the thermal protection circuit could operate. 11. unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the pins because the device might be damaged, which could happen due to negative voltage or excessive voltage generated during the on and off timing when the inductive load of a motor coil or actuator coils of optical p ick-up is being driven. 12. verify the risks which might be caused by the malfunctions of external com ponents. d o c n o . t a4 - ea - 04725 r e v i sio n . 3 e s t a b li s h e d : 2007 - 05 - 24 r e v i s e d : 2013 - 04 - 15
request for your special attention and precautions in using the technical information and semiconductors described in this book (1) if any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) the technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. no license is granted in and to any intellectual property right or other right owned by panasonic corporation or any other company. therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) the products described in this book are intended to be used for general applications (such as office equipment, communications equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book. consult our sales staff in advance for information on the following applications: ? special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. it is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with your using the products described in this book for any special application, unless our company agrees to your using the products in this book for any special application. (4) the products and product specifications described in this book are subject to change without notice for modification and/or im- provement. at the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date product standards in advance to make sure that the latest specifications satisfy your requirements. (5) when designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. otherwise, we will not be liable for any defect which may arise later in your equipment. even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (esd, eos, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. when using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) this book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20100202

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